Method for the manufacture of a Schottky gate field effect transistor

ABSTRACT

In the manufacture of a Schottky gate field effect transistor, an insulating film is deposited on the main surface of a semiconductor substrate and is then selectively removed to form therein a window through which the substrate surface region for forming an active layer is exposed to a space in which the gate will ultimately be provided. A metal which forms a Schottky junction between it and the semiconductor of the active layer and can be removed by anisotropic etching and a metal which can be used as a mask for the etching of the above metal are deposited in layers on the insulating film and the substrate surface exposed through the window. The overlying metal layer thus deposited is planarized to leave in the window alone. The underlying metal layer is selectively removed by anisotropic etching through the overlying metal layer remaining in the window, thus forming a gate electrode made up of the overlying and underlying metal layers. The structure thus obtained is small in the overlapping of the gate electrode on the adjoining insulating films, ensuring the reduction of parasitic capacitances to thereby speed up the operation of the device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for the manufacture of a fieldeffect transistor which has an active layer of a gate region andion-implanted source and drain regions formed in the main surface of asemiconductor substrate.

2. Description of the Prior Art

A Schottky junction gate type field effect transistor (hereinafterreferred to as an MESFET) utilizing a compound semiconductor such asGaAs has been employed widely as a discrete semiconductor component partfor a high frequency, an oscillator, and so forth; at present, it isplaying an important role as a basic element of high frequency and highspeed integrated circuits as well. As is well-known in the art, the highfrequency performance of such an MESFET is described in the form of aratio, Gm/Cg, where Gm and Cg are its transconductance and gatecapacitance, respectively. The high frequency performance could beimproved by increasing the transconductance Gm relative to the gatecapacitance Cg. It is well-known that the effective transconductance Gmof the MESFET is given by Gm=Gm₀ /(1+Gm₀ ·Rs), where Gm₀ is theintrinsic transconductance dependent upon the characteristic of thechannel part and Rs is the parasitic series resistance between thesource and gate. As seen from the above, the presence of the parasiticseries resistance Rs makes the effective transconductance Gm smallerthan the intrinsic transconductance Gm₀. Accordingly, how to reduce theparasitic series resistance Rs is a key for obtaining a largetransconductance to improve the high frequency performance.

A known technique for diminishing the parasitic series resistance Rs isself-alignment technology for the formation of the gate-Schottkyjunction and the source and drain regions. This can be achieved inseveral ways; a typical example is shown in FIG. 9 (K. Yamasaki et al.,Electron Lett. 18(3), (1982), pp 119-121). An N type impurity, forexample, silicon is selectively ion implanted into the main surface of aGaAs or semi-insulating compound semiconductor substrate 11, formingtherein a primary ion-implanted layer 12 which will ultimately serve asan active layer (FIG. 9A). A silicon nitride film 13 is deposited 0.15μm thick all over the main surface of the substrate 11 through plasmaCVD method, for instance. Further, a resist layer 14 of a tri-levelstructure made up of, for example, a resist film 14₁, an insulating film14₂ as of SiO₂, and a resist film 14₃ is formed on the silicon nitridefilm 13.

Next, the uppermost resist film 14₃ of the tri-level resist layer 14 ispatterned by photolithography, after which the intermediate insulatingfilm 14₂ and the lower most resist film 14₁ are selectively removed insuccession by reactive ion etching or the like using the patternedresist film 14₃ as a mask, whereby apertures are made in a region whereto provide the source and drain, thus partly exposing the siliconnitride film 13 through the apertures. Following this, an N typeimpurity, for instance, silicon, is selectively ion implanted into thesubstrate 11 through the tri-level resist layer 14 acting as a mask, bywhich is formed high impurity concentration ion-implanted layers 15having an impurity concentration approximately 10 times higher than thatof the primary ion-implanted layers 12 (FIG. 9B). Then a SiO₂ film 16 isdeposited, for example, 0.3 μm thick over the entire area of the mainsurface of the substrate 11. Thereafter, the SiO₂ film 16 deposited onthe tri-level resist layer 14 alone is removed by a lift-off processtogether with the latter, leaving the SiO₂ film 16 on the siliconnitride film 13 except for the portion covered with the lowermost resistfilm 14₁ (FIG. 9C). As a result of this, the SiO₂ film 16 remainsunremoved almost right above each of the high impurity concentrationion-implanted layers 15. In this instance, if the tri-level resist layer14 is selectively etched in such a T-letter shape, as a whole, that thelowermost resist film 14₁ is side-etched as compared with theintermediate film 14₂, as depicted in FIG. 9B, then the abovesaid SiO₂film 16 will be formed overhanging the inner end of each high impurityconcentration ion-implanted layer 15 accordingly. Next, the substrateassembly is annealed, for instance, in an N₂ atmosphere at 800° C. for20 minutes for activating the ion-implanted layers 15. After this, aresist pattern which has windows on positions corresponding to sourceand drain electrodes is formed all over the main surface of thesubstrate 11 with the silicon nitride film 13 and the SiO₂ film 16deposited thereon. The silicon nitride film 13 and the SiO₂ 16 areselectively removed by, for example, reactive ion etching and plasmaetching through the resist pattern. Following this, an ohmic contactelectrode material, for instance, AuGe/Ni, is vacuum evaporated throughthe above resist pattern and then lifted off together with the resistpattern, after which the remaining portions of the deposited metal arealloyed, providing a source electrode 17 and a drain electrode 18. Next,a resist pattern which has a window only at a position corresponding toa gate electrode is deposited all over the main surface of the substrate11, through which pattern the silicon nitride film 13 is selectivelyetched away to expose the surface of the ion-implanted layer 12, throughan etching process which etches the silicon nitride film 13 at a higherrate than the SiO₂ film 16, such as the plasma etching or reactive ionetching process. Next, a metal which will form a Schottky junctionbetween it and the GaAs substrate 11 is deposited on the exposed surfaceof the ion-implanted layer 12 and an unnecessary part of the depositedmetal is lifted off together with the resist pattern, thus forming agate electrode 19 (FIG. 9D).

The self-aligned MESFET thus obtained is, however, defective in that thegate electrode 19 overrides the insulating film 16 on either sidethereof. With such a structure, the capacitance Cg between the gateelectrode 19 and the channel layer is given by Cg=Cj+2Cp, i.e. the sumof the junction capacitance Cj and a parasitic capacitance Cp bwtweenthe electrode portion overriding the insulating layer 16 and thechannel, as schematically shown in FIG. 10. In this case, an increase inthe capacitance Cg will degrade the high frequency and high speedcharacteristics of the device, impairing the performance of the GaAs IC.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a fieldeffect transistor manufacturing method which permits the reduction ofthe overlapping of the gate electrode and the adjoining insulating filmsso that the parasitic capacitances resulting from the above overlappingis eliminated for speeding up the operation of the field effecttransistor.

According to the present invention, in the self-aligned formation of thegate electrode, an insulating film is deposited all over the mainsurface of a semiconductor substrate and is then selectively removed toform therein an aperture through which an active layer in the substrateis exposed to a space where to form a gate. A composite layer, which ismade up of an underlying layer of a metal which forms a Schottkyjunction between it and the semiconductor substrate and can be removedby anisotropic etching and at least one overlying layer of a metal whichcan be used as a mask for the etching of the above-said underlying metallayer, is deposited as a layer of gate metal, filling up the aperture.Then the surface of the overlying metal layer is planarized and/or it isfurther overetched so that the overlying metal layer remains in theaperture. The underlying metal layer is selectively removed byanisotropic etching through the overlying metal remaining in theaperture, thus forming the gate electrode on the exposed active layer.

In general, the aperture made in the insulating film gradually spreadsopen upward. On the other hand, according to the method described above,when the aperture is filled up with the composite layer as the gatemetal layer and the layer is planarized, the overlying metal layerremaining in the aperture lies on the exposed surface of the activelayer where to form the gate electrode, and the width of the overlyingmetal layer is smaller by the thickness of the underlying metal layerdeposited on the side walls of th insulating film. Accordingly, byproperly controlling the thickness of the underlying metal layer, thewidth of the remaining overlying metal layer can be made equal to thefoot width of the exposed surface of the active layer on which the gateelectrode is to be formed.

In the event that the width of the remaining overlying metal layercannot be made equal to the foot width of the gate electrode formingportion through the thickness control of the underlying metal layeralone the overlying metal layer after being planarized is over-etched sothat its both marginal edges are etched back, thereby making the bothwidths equal to each other.

Thereafter, by the abovesaid anisotropic etching of the underlying metallayer through the remaining overlying metal layer substantially matchedwith the foot width of the aperture for the gate electrode formingportion, the required gate electrode can be formed on a self-alignedbasis with practically no overlapping on the adjoining insulating films.

As described above, according to the present invention, the overlappingof the gate electrode on the surrounding insulating films is avoidedthrough control of the thickness of the underlying metal layer orover-etching of the overlying metal layer. That is to say, the presentinvention eliminates parasitic capacitances resulting from the abovesaidoverlapping, and hence enables a high speed operation of the fieldeffect transistor.

Other objects, features and advantages of the present invention willbecome more fully apparent from the following detailed description takenin conjuncion with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, B and C are sectional views and a plan view for explaining theconcept of the present invention;

FIGS. 2A and B are cross-sectional views for explaining the principlesof the present invention;

FIGS. 3A, B and C are cross-sectional views for further explaining theprinciples of the present invention;

FIGS. 4A through G are cross-sectional views illustrating a sequence ofsteps involved in an embodiment of the present invention;

FIGS. 5A through D are cross-sectional views illustrating a sequence ofsteps involved in another embodiment of the present invention;

FIGS. 6A and B are a diagram for explaining the definition of an ionbeam incident angle and a graph showing the relationship between the ionbeam incident angle and the etching rate;

FIG. 7 is a diagram for explaining the principle of planarization;

FIG. 8 is a diagram showing how planarization takes place in anembodiment of the present invention;

FIGS. 9A through D are cross-sectional views showing a sequence of stepsinvolved in a conventional manufacturing method; and

FIG. 10 is a schematic cross-sectional view illustrating a conventionaldevice.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will be given first, with reference to FIG. 1, of aself-aligned gate electrode forming method according to the presentinvention. In FIG. 1 the internal structure of a semiconductor substrate1 is not shown for the sake of brevity. The formation of such a gateelectrode starts with the depostion of insulating films 2 and 3 over theentire area of the semiconductor substrate 1 so that they cover itssurface region where source and drain regions will ultimately be formed,and the insulating layers 2 and 3 overlying the surface region of thesubstrate 1 where an active layer will ultimately be formed areselectively removed so as to form an Schottky contact region. A metalfilm 4, which forms a Schottky junction between it and the semiconductorsubstrate 1 and can be removed by anisotropic etching such as reactiveion etching, is deposited all over the main surface of the semiconductorsubstrate 1 covered with the insulating films 2 and 3. Then an overlyingsingle- or multi-layer metal film 5, which can be used as a mask for theanisotropic etching of the metal film 4, is deposited thereon. Theovelying metal film 5 is planarized so that it remains only in therecess defined by the insulating films 2 and 3 (FIG. 1A), and theunderlying metal film 4 is removed by reactive ion etching or similaranisotropic etching through the overlying metal layer 5 remaining in therecess. In this way, the gate electrode can be formed only in therecessed region of the insulating films 2 and 3 indicated by a footwidth b. By employing such a two-layered structure for the gateelectrode, it is possible to obtain a structure in which the gateelectrode and the insulating films 2 and 3 do not overlap at all, asshown in FIG. 1B, even when the inner ends of the insulating film 3 arenot steep. That is, the aperture width c of the recessed region definedby the insulating films 2 and 3 decreases by the thickness of theunderlying metal film 4 deposited on the side walls of the insulatingfilms 2 and 3. Accordingly, when the overlying metal layer 5 is leftonly in the recessed region by its planarization after being deposited,the width a of the overlying metal layer 5 becomes smaller than thebefore-mentioned width c. Moreover, letting the foot width of theexposed active layer be represented by b, the underlying metal film 4has such a thickness that a=b. In this instance, colective removal ofthe underlying metal film 4 by anisotropic etching through the overlyingmetal layer 5 remaining in the recessed region will provide such astructure as depicted in FIG. 1B which is entirely free from overlappingof the gate electrode and the insulating films 2 and 3. Furthermore,according to this manufacturing method, since the material forplanarization is also metal, the cross-sectional area of the gate metalremaining in the recessed region is larger than in the case of usingresist or an insulating film such as a nitride film for planarization(Japanese Patent Application No. 247019/74, for example); this bringsabout the advantage of lowered gate resistance as well. FIG. 1C is aplane view of the structure shown in FIG. 1B, which the insulating filmsare partly removed and source and drain electrodes 6 and 7 are provided.The gate electrode 5 is let out and a pad 8 is mounted thereon.

FIG. 2 illustrates in cross-section the structure in which a metalcapable of acting as a mask for reactive ion etching or the like isdeposited as the overlying metal layer 5 and is planarized. As depictedin FIG. 2A in which the thickness of the underlying metal layer 4 isrepresented by d, the width a of the gate electrode 5 can be madesubstantially equal to the foot width b by optimizing the relationshipbetween the angle of inclination of the side wall of the recess and thethickness of an insulating film 20 (indicating both of the films 2 and 3in FIG. 1), or by determining conditions through preliminaryexperiments. As depicted FIG. 2B by selectively removing the metal film4 by anisotropic etching such as reactive ion etching through the metallayer 5, the gate electrode can be formed only on the region indicatedby the foot width b of the insulating film 20, with the marginal edgesof the gate electrode tapering off at the upper edges of the insulatingfilm 20.

As illustrated in FIG. 3, however, the case where the recess in theinsulating film 20 is not sharp in its cross-sectional profile, that is,where the inner edges of the insulating film 20 are dull, the overlyingmetal layer 5 on the underlying metal film 4, when planarized, willoverlap the insulating film 20, as indicated by a' in FIG. 3A. In thiscase, if the underlying metal film 4 is subjected to anisotropic etchingthrough the overlying metal layer 5, then the pattern of the metallayers 4 and 5 will override the insulating film 20, as depicted in FIG.3B, developing parasitic capacitances.

Also in the case of FIG. 3B, however, the overlaps of the pattern on theinsulating film 20 are smaller than in the conventional method whichforms the gate electrode 19 by depositing the metal for forming theSchottky junction and patterning it after removing its unnecessaryportion, as described previously with respect to FIG. 9. The reason forthis is that the method of the present invention does not call for anallowance for mask alignment for the patterning of the metal layer 4unlike in the case of the conventional method shown in FIG. 9. In thestructure depicted in FIG. 3B, however, it is desirable, for furtherreduction of the parasitic capacitances, to prevent the gate electrodefrom overriding the insulating film.

To meet this requirement, it is necessary only to etch back the metallayer 5 to such a depth that its width a becomes equal to the foot widthb of the recess in the insulating film 20. Thereafter, by selectivelyremoving the underlying metal layer 4 through anisotropic etching, usingthe metal 5 (hatched with solid oblique lines), a patter shown in FIG.3C can be obtained, in which the metals 4 and 5 are formed in the recesswithin its foot width b alone. As will be appreciated from the above, inthe present invention the planarization of the overlying metal is meansby which the end portions of the insulating layer and the marginal edgesof the gate metal are substantially aligned with each other. There arecases where the above positioning can be achieved by such aplanarization step alone, but when the positioning is insufficient onlywith the planarization step, the afore-mentioned etch-back oroveretching step is carried out.

As will be evident from comparison of the structures shown in FIGS. 2Aand 3C, the thickness of the overlying metal layer 5 relative to thethickness of the underlying metal layer 4 in FIG. 3C is smaller than inthe case of FIG. 2A. This means that when a low resistance metal such asgold (Au) is used for the overlying metal layer 5, the effect ofdecreasing the resistance will be lessened accordingly.

It is therefore desirable that the recess or window made in theinsulating film 20 have as steep side walls as possible.

It is also possible, in practice, to make sharp the cross-sectionalprofile of the recess by controlling the thickness of the underlyingmetal layer 4 and to etch back the overlying the metal layer 5, asreferred to previously with regard to FIG. 3, thereby making the footwidth b of the recess and the width a of the overlying metal layer 5equal to each other.

FIG. 4 illustrates, in cross-section, a sequence of steps involved inthe manufacture of a field effect transistor according to an embodimentof the present invention, in which the semiconductor substrate is a GaAssubstrate.

At first, for example, silicon which will act as an N type impurity ision implanted into the main surface of a semi-insulating GaAs substrate41 in a dose of 1×10¹² /cm² under an acceleration voltage of 60 KeV,through a 1.2 μm thick photoresist film (not shown), thereby forming aprimary ion-implanted layer 42 in the substrate 41 (FIG. 4A). Next, asilicon nitride film 43 is deposited 0.15 μm thick all over the mainsurface of the substrate 41 through the plasma CVD method, after whichis formed by the reactive ion etching or the like a tri-level resistlayer 44 which is open only at the portions corresponding to thesubstrate surface regions where the source and drain regions willultimately be formed (in the same manner as in the case of FIG. 9B).Then, for example, silicon which will act as an N type impurity is ionimplanted into the substrate 41 in a dose of 4×10¹³ /cm² under anacceleration voltage of 200 KeV, using the multi-level resist layer 44as a mask, by which high impurity concentration ionimplanted layers 45is formed (FIG. 4B). Following this, for instance, a SiO₂ film isdeposited, by sputtering or the like, to a thickness of 3000 Å all overthe main surface of the substrate 41 carrying the multi-level resistlayer 44. Then the SiO₂ film on the multi-level resist layer 44 islifted off together with the latter, thereby forming on the siliconnitride film 43 a SiO₂ film 46 of a pattern inverted from that of thelowermost resist film of the multi-level resist layer 44 (FIG. 4C). Foractivating the ion-implanted layers 42 and 45, the substrate assembly isannealed, for instance, in an N₂ atmosphere at 800° C. for 20 minutes.

Next, the silicon nitride film 43 is selectively removed by plasmaetching or reactive ion etching through the SiO₂ films 46, exposing theprimary ion-implanted layer 42. A metal which forms a Schottky junctionbetween it and the GaAs and can be removed by anisotropic etching, suchas molybdenum (Mo), is deposited, by sputtering, to a thickness of 1500Å all over the main surface of the substrate 41, as indicated by 47.Further, a metal which is capable of serving as a mask for the etchingof the underlying metal layer 47, such as gold (Au), is deposited bysputtering to a thickness of 4000 Å all over the molybdenum layer 47, asindicated by 48 (FIG. 4D). Then the surface of the gold layer 48 isplanarized. Several methods can be employed for the planarization. Forexample, the surface of the gold layer 48 is planarized by etching itback through an ion beam etching process in which beam incident angleis, for instance, 60° or more. As a result of this, the gold layer isleft remaining only in the recessed region defined by the SiO₂ films 46,as indicated by 48₁ (FIG. 4E).

According to the above method, the convexity of the layer surface canselectively be etched away for planarization through utilization of thedependence of the etching rate upon the ion beam incident angle.

Where the ion beam incident angle is defined in terms of an angle θ tothe normal to the substrate, as shown in FIG. 6A, the beam incidentangle dependence of the etching rate by the ion beam etching differswith materials to be etched, which are roughly divided into those theetching rate of which is maximum when the ion beam is incidentvertically thereto (θ=0) (as indicated by 31 in FIG. 6B), such a gold(Au), and those the etching rate of which is maximum when the ion beamis incident in the range of θ=40° to 60° (as indicated by 32 in FIG.6B), such a silicon (Si). In either case, when the ion beam incidentangle θ is in excess of 60°, the etching rate decreases with an increasein the incident angle and becomes zero at 90°. Accordingly, in the caseof etching back a layer having a surface step by an ion beam incident atan angle θ, as depicted in FIG. 7, the incident angle θ to the slope ofthe surface step is smaller than the angle θ and there exists anincident angle θ at which the etching rate R (θ) on the slope of thesurface step is higher than the etching rate R (θ) on the flat surfaceportion owing to the ion beam incident angle dependence of the etchingrate and the shape of the surface step. By etching back at this incidentangle the thin film of the convexity can selectively etched away (whichetching will hereinafter be called diagonal ion beam etching).

FIG. 8 shows how the diagonal ion beam etching is carried out in anembodiment of the present invention, in which layer surfaces areplanarized as indicated by i, ii, and iii.

Turning back to FIG. 4, the underlying molybdenum (Mo) layer 47 isselectively etched away through the gold (Au) layer 48₁ by reactive ionetching using CF₄ or SF₆ gas, thus forming a gate electrode (FIG. 4F).

Next, a resist pattern which has openings at positions correspondingonly to the portions where to form source and drain electrodes isdeposited on the main surface of the substrate 41, though not shown, andthen the SiO₂ films 46 and the silicon nitride films 43 are selectivelyremoved by reactive ion etching and plasma etching, respectively,through the abovesaid resist pattern. Following this, an AuGe/Ni layeris vacuum evaporated as an ohmic metal layer to a thickness of 0.13 μmthrough utilization of the resist pattern as a mask and is then liftedoff and the remaining portions of the layer are alloyed, forming sourceand drain electrodes 49₁ and 49₂ (FIG. 4G).

With the structure thus obtained, the gate electrode does not overridethe insulating films adjoining the gate and the inner ends of theaperture made in the insulating film and the outer side walls of thegate electrode portion are just in contact with each other; so that noparasitic capacitances are developed between the electrode portion andthe channels. This ensures improvement of the high frequency and highspeed characteristics of the device.

FIG. 5 illustrates another embodiment of the present invention. Thestructures depicted in FIGS. 5A and 5B are identical with those shown inFIGS. 4A and 4B and the same reference numerals are used. In FIG. 5C,the overhanging portion of the T-shaped multi-level resist layer 44 isremoved, after which the SiO₂ film 46 is deposited by sputtering, asshown in FIG. 5D. In this instance, since the multi-level resist layer44 has no overhanging portion, the inner marginal edges of the SiO₂ film46 can be made sharper than in the case of the method described inconnection with FIG. 4. This is advantageous for forming a thick lowresistance gold (Au) layer in the subsequent steps (which are the sameas those shown in FIGS. 4D through G), as mentioned previously withrespect to FIG. 2.

While the above embodiments have been described to employ molybdenum(Mo) as the underlying metal which is capable of forming a Schottkyjunction between it and the semiconductor used and can be removed byanisotropic etching, it is possible, of course, to use other metals ofsimilar functions, such as tantalum (Ta). Further, tungsten silicide andtungsten silicon nitride can also be utilized.

Although the present invention has been described in connection with itspreferred embodiments, it is apparent that many modifications andvariations may be effected without departing from the spirits of thepresent invention recited in the appended claims. According to thepresent invention, the self-aligned formation of the gate electrode of afield effect transistor sharply reduces or eliminates the overriding ofthe gate electrode metal on the adjoining insulating films, permitting asubstantial reduction of the parasitic gate capactiance. Accordingly,the manufacturing method of the present invention offers an excellentfield effect transistor possible of high frequency and high speedoperation as compared with field effect transistors produced by priorart methods.

What is claimed is:
 1. A method for the manufacture of a field effecttransistor, comprising:a step wherein a source region, a drain region,and an active region sandwiched therebetween are formed in the body of asemiconductor substrate near its one main surface and an insulating filmof at least one layer deposited all over the main surface of thesubstrate is selectively removed, exposing a part of the active regionformed in the semiconductor substrate; a step wherein an underlyingmetal which forms a Schottky junction between it and the semiconductorof the active region and can be removed by anisotropic etching and anoverlying metal of at least one layer which is capable of serving as amask for the etching of the underlying metal are deposited in layers onthe insulating film and the substrate surface exposed through theaperture made in the insulating film, filling the aperture with theunderlying and the overlying metal; as step wherein the surface of theoverlying metal layer is planarized so that the overlying metal layerselectively remains in the aperture of the insulating film; a stepwherein the underlying metal layer is selectively removed by anisotropicetching through the remaining the overlying metal, forming a gateelectrode of the overlying and underlying metal layers on the activeregion exposed through the aperture of the insulating film; and a stepwherein the insulating film is partly removed and source and drainelectrodes are formed on the source drain regions, respectively.
 2. Themanufacturing method according to claim 1 wherein the thickness of theoverlying metal layer is controlled so as to control the width of theoverlying metal layer remaining in the aperture of the insulating film.3. The manufacturing method according to claim 1 wherein after theplanarization of the overlying metal layer its surface is futherover-etched to back its upper marginal edges.
 4. The manufacturingmethod according to claim 1 further including a step wherein amulti-level resist layer is formed on one main surface of thesemiconductor substrate and patterned to expose the surface regions ofthe semiconductor substrate where the source and drain regions willultimately be formed, an impurity which will form the source and drainregions is ion implanted using the multi-level resist layer as a mask,an insulating film is deposited on the main surface of the semiconductorsubstrate, and the insulating film overlying the multi-level resistlayer is lifted off together with the latter, thereby leaving on themain surface of the semiconductor substrate the insulating surface in apattern inverted from that of the lowermost resist film of themulti-level resist layer.
 5. The manufacturing method according to claim4 wherein overhanging portions of the multi-level resist layer areremoved after the ion implantation of the impurity through themuli-level resist layer.
 6. The manufacturing method according to claim1 wherein the underlying metal layer is formed of molybdenum (Mo),tantalum (Ta), tungsten silicide, or tungsten silicon nitride.